1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device with an alternative strapped wordline architecture and to a method for its fabrication.
2. Description of the Related Art
Semiconductor devices are widely used in various types of electronic products, consumer products, printed circuit cards, and the like. In an integrated circuit, a number of active semiconductor devices are formed on a chip ("die") of silicon and the chip circuit is interconnected to packages leads to form a complete circuit. In the design of Very Large Scale Integrated (VLSI) circuits, dynamic logic cells which are maintained in integrated circuits in a space efficient manner and which improve the speed of read operations by making array row and column selection faster is a goal sought by designers. The improvement in the speed of read and write operations for dynamic logic cells utilized in memory designs reduces delays in processing which, in turn, increases performance of the overall system. Additionally, any reduction in the size of the package can provide a significant commercial advantage.
Semiconductor memory devices such as a random access memories (RAM) comprise an array of individual memory cells. A RAM allows the user to both read information from the memory and to write new information into the memory. Data is read from the memory by activating a row, referred to as a wordline, which couples all memory cells corresponding to that row to active digit or bit lines which define the columns of the array. When a particular wordline is activated, sense amplifiers connected to an active bit line detect and amplify the data by measuring the potential difference between the activated bit line and a reference.
FIG. 1 illustrates a block diagram of a typical memory bank architecture. Memory bank 10 consists of parallel memory arrays 20, 21, 22, 23. Each of the memory arrays 20-23 comprises a plurality of memory cells (not shown), arranged in 2.sup.M columns by 2.sup.N rows. Each of the memory cells located in the same row of the array are coupled together by a wordline, as illustrated by wordlines 30, 31, 32, 33. Each of the wordlines 30-33 of the respective arrays 20-23 are connected to a respective row decoder 50, 51, 52, 53, 54. Each of row decoders 50-54 contains row driver circuitry 55, which activates the desired wordline 30-33 of the respective array 20-23 of the cell desired to be accessed. Row decoders 50, 52 and 54 are designated as even row decoders, and row decoders 51 and 53 are designated as odd row decoders. A respective column decoder 40, 41, 42, 43 is provided for each array 20-23 to access the particular column or columns desired.
In order to maintain a consistent time constant associated with accessing any of the cells in the arrays, a row decoder is provided adjacent to each side of each memory array and the wordlines of each respective array are connected to a row decoder located directly adjacent to each array. This minimizes the delays in signal propagation through each wordline since the row decoders are evenly distributed throughout the array.
Thus, as shown in FIG. 1, the even wordlines of each array are connected to the closest adjacent even row decoder, while the odd wordlines of an array are connected to the closest adjacent odd row decoder. For example, even wordline 30 of array 21 is connected to even row decoder 52, odd wordline 31 of array 21 is connected to odd row decoder 51, even wordline 32 is connected to even row decoder 52, odd wordline 33 is connected to odd row decoder 51, etc. This requires an odd row decoder and an even row decoder to be positioned directly adjacent to each side of each of the arrays. A typical row decoder gap requires approximately 250 .mu.between each array, with some row decoders requiring up to 350 .mu.between each array. Thus, the amount of space required only by the row decoders could be as much as 1,750 .mu.m for each memory bank that consists of four arrays as illustrated by memory bank 10.
This space significantly increases the overall physical space required by a memory device which consists of several memory banks 10 as depicted in FIG. 1.
Additionally, the number of row decoders of the conventional memory bank could not be decreased by connecting wordlines of one array to a row decoder through the wordline of another array. For example, if wordline 30 of array 21 was connected to row decoder 50 through wordline 30 of array 20, thus eliminating the need for row decoder 52, the propagation delay associated with the polysilicon used for each wordline would cause delays in accessing the cells located in wordline 30 of array 21. The delay associated with the propagation of a signal through both wordlines 30 of arrays 21 and 20 may be significant enough to affect the speed of the memory bank 10, rendering the memory bank 10 unusable in high speed end systems.
Thus, there exists a need for an alternative memory architecture that reduces the amount of space necessary for the row decoders while also maintaining the system time constant associated with accessing any cell in the entire bank. Additionally, sufficient space must be provided between the wordlines, or any other connections to the row decoders, to prevent them from shorting together, rendering the memory bank defective.